The invention lies in the semiconductor technology field. More specifically, the invention relates to a method for testing a semiconductor memory, in which a predetermined data value is written to a memory cell, read out and compared with the data value that has been read out in order to buffer-store the comparison result in another portion of the memory cells for a subsequent redundancy analysis. The invention further relates to a semiconductor memory with a test device which controls such a memory test.
In order to check the functionality of a semiconductor memory after the latter has been fabricated, the individual memory cells are tested. Defective memory cells are subsequently replaced by redundant memory cells in order to establish full functionality. During the functional test, a predetermined data value is written to the memory cells and is subsequently read out and compared with the predetermined data value. Due to the fact that the data input and output bandwidth between semiconductor chip and automatic test machine constitutes a bottleneck, endeavors are made to ensure that as many test steps as possible run on the semiconductor chip itself, without the need to communicate with the automatic test machine.
Commonly assigned German patent application DE 197 25 581 A1 describes a method for testing a semiconductor memory and also a corresponding semiconductor memory, in which a so-called bit fail map is created by comparing written data and desired values for a first area of the memory. The bit fail map is buffer-stored in up to three copies on the semiconductor chip in other, as yet untested memory areas. During read-out, a comparison is made of all three copies of each of the test results in the bit fail map. The value which occurs the most often is used further. A redundancy analysis in which the bit fail map is processed further is used to determine which defective memory cells are to be replaced by redundant memory cells, so that as far as possible all defects can be eliminated and the memory can be found to be functional.
The functional defects of a semiconductor memory generally do not occur in uniform distribution over the memory cell array, but rather accumulate along columns or rows of the matrix-like memory cell array. If, by way of example, a defect occurs in an address decoder, the result of this is that all the memory cells of the word lines affected by the defect can no longer be accessed. If one of the word lines is interrupted, it is no longer possible to access a portion of the memory cells which are addressed by the respective word line. Defects occur in a corresponding manner in memory cells connected to a bit line, if the bit line, the read/write amplifier assigned to the bit line, or that part of the address decoder which decodes the bit line are defective.
Even though the bit fail map is stored multiple times in as yet untested memory areas in the method described in the published application DE 197 25 581 A1, there is nevertheless the risk of a plurality of copies of the bit fail map being interfered with in the same sense on account of a uniform defect extending along a row or column. Despite a majority decision during read-out of the bit fail map, incorrect defect data are processed further. The supply of redundant memory cells is usually used up earlier than necessary. On the other hand, it can happen that defective memory cells are not identified as such.
It is accordingly an object of the invention to provide a semiconductor memory test method and a semiconductor memory with a test device, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which yields more reliable test results.
A further object of the invention is to specify a corresponding semiconductor memory with a test device which controls the test sequence.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method of testing a semiconductor memory with a plurality of memory banks, which comprises the following steps:
writing a predetermined data value to a memory cell of a first portion of memory cells in a first memory bank of a semiconductor memory;
reading out the data value from the memory cell, comparing the read-out data value with the predetermined data value, and determining a data value for a comparison result;
buffer-storing the data value for the comparison result in a memory cell in another portion of memory cells in a second memory bank of the semiconductor memory;
reading out the stored data value for the comparison result and carrying out a redundancy analysis in which defective memory cells of the first portion of memory cells are replaced by redundant memory cells.
In other words, the novel method provides for the memory cells to be tested to be arranged in a first memory bank, and the defect data to be stored on the chip be buffer-stored in memory cells of a second, other memory bank. This is based on the consideration that memory banks are memory areas that can be operated autonomously and independently of one another and the defects in different memory banks can therefore be regarded as independent of one another. In particular, row and column defects do not propagate from one memory bank to another memory bank. This is because memory banks have address decoders and read/write amplifiers which access only memory cells of precisely this memory bank. Bit lines and word lines within a memory bank extend exclusively only within precisely this memory bank. If values of the bit fail map in a memory bank are corrupted by defects present therein, it can normally be assumed that the same memory cells in another memory bank are not defective.
In accordance with an added feature of the invention, the data value for the comparison result is stored in parallel in at least three memory cells arranged in respectively different memory banks. Generally, the bit fail map is stored an odd number of times, in respective different memory banks. In all probability, corruption of one copy of the bit fail map in one memory bank will not occur at the same location in another memory bank. The correct defect information is obtained by means of a majority decision applied to corresponding values, originating from the same memory cell to be tested, of different copies of the bit fail map from different memory banks.
In accordance with an additional feature of the invention, the at least three data values of the comparison result stored in parallel are read out, and a single data value is determined from the at least three data values by means of a majority decision, and the single data value is subsequently fed to the redundancy analysis.
In accordance with another feature of the invention, each memory bank comprises an address decoder for selecting memory cells only of the respective memory bank.
With the above and other objects in view there is also provided, in accordance with the invention, a semiconductor memory, comprising:
a plurality of memory banks including a first memory bank and at least one second memory bank, each memory bank having memory cells;
a test device connected to the memory banks and programmed to test the semiconductor memory by writing a predetermined data value to a memory cell of the first memory bank, reading out the data value from the memory cell of the first memory bank, comparing the read-out data value with the predetermined data value in order to determine a data value for the comparison result, by buffer-storing the data value for the comparison result in a memory cell of the second memory bank, and by reading out the stored data value for the comparison result for carrying out a redundancy analysis.in which defective memory cells of the first memory bank are replaced by redundant memory cells.
In accordance with a further feature of the invention, each memory bank comprises an address decoder for selecting memory cells, and the address decoder is adapted to only select the memory cells of the respective memory bank.
In accordance with again an added feature of the invention, the plurality of memory banks are at least three memory banks each containing memory cells, and the test device is adapted to store the data value for the comparison result in parallel in a respective memory cell of the three memory banks.
In accordance with again a further feature of the invention, the test device is adapted to determine, from the data values for the comparison result read from the different memory banks, a single data value with a majority decision and to feed the single data value to the redundancy analysis.
In accordance with a concomitant feature of the invention, a changeover device is connected to each memory bank, the changeover device containing a multiplexer and a demultiplexer, the changeover device is connected to receive a respective address for selecting a memory bank, a terminal for a data signal of the memory bank connected to the output of the multiplexer and the input of the demultiplexer, the input of the multiplexer and the output of the demultiplexer each being connected to a signal line for the predetermined data value to be stored and the data value to be read out subsequently, and to a signal line for the data value for the comparison result to be written and to be read out subsequently.
Different memory banks operate independently of one another. In conventional memory architectures, different memory banks can be accessed simultaneously in the same timing cycle. One access cycle suffices, therefore, for storing a plurality of copies of the bit fail map in different memory banks. During the storage of the bit fail map, it is actually possible, in the memory bank to be tested, to test a further memory cell (or else groups of memory cells, depending on the organization of the test), whose test result is stored once again in the different memory banks in the subsequent access cycle. Since the bit fail map is determined iteratively and writing and reading are effected multiple times during the test, there is a considerable increase in the test speed by comparison with the method described in the above-mentioned published patent application DE 197 25 581 A1.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for testing a semiconductor memory, and semiconductor memory with a test device, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.